1. Field of the Invention
This invention is related to the field of processors and, more particularly, to speculatively fetching instructions following a branch instruction in a microprocessor.
2. Description of the Related Art
Superscalar processors attempt to achieve high performance by issuing and executing multiple instructions per clock cycle and by employing the highest possible clock frequency consistent with the design. Over time, the number of instructions concurrently issuable and/or executable by superscalar processors has been increasing in order to increase the performance of superscalar processors.
Unfortunately, many of the concurrently issuable and/or executable instructions are branch instructions where the address of the instruction subsequent to the branch instruction may not be known prior to execution of the branch instruction. Consequently, branch instructions may incorporate significant delays into a superscalar microprocessor.
One mechanism to counter the delays caused by branch instructions is a branch prediction unit. A branch prediction unit is typically configured to provide a branch prediction address in response to receiving the address of a branch instruction. In order to generate a branch prediction address, however, a branch instruction typically must be fetched and decoded. After a branch instruction is fetched and decoded, a branch prediction unit must then spend one or more clock cycles generating a branch prediction address. Although a branch prediction unit reduces the delay associated with branch instructions, significant delays still occur between fetching a branch instruction and generating a corresponding branch prediction address. It would be desirable to minimize the time between fetching a branch instruction and generating a branch prediction address.